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2(
2(/:(
2(
:(
:( Negation-Address Delay (A6TEH2–A6TEH0): These bits set the address
:(
Bits 2 to 0—2(
hold delay time from 2(/:( negation in a write on the connected PCMCIA interface or in an I/O
card read. In the case of a memory card read, the address hold delay time from the data sampling
timing is set. The setting of these bits is selected when the PCMCIA access TC bit is set to 1.
Bit 2: A6TEH2
0
1
13.2.8
Synchronous DRAM Mode Register (SDMR)
The synchronous DRAM mode register (SDMR) is a write-only virtual 16-bit register that is
written to via the synchronous DRAM address bus, and sets the mode of the area 2 and area 3
synchronous DRAM.
Settings for the SDMR register must be made before accessing synchronous DRAM.
Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Since the address bus, not the data bus, is used to write to the synchronous DRAM mode register,
if the value to be set is "X" and the SDMR register address is "Y", value "X" is written to the
synchronous DRAM mode register by performing a write to address X + Y. When the
synchronous DRAM bus width is set to 32 bits, as A0 of the synchronous DRAM is connected to
A2 of the SH7750 Series, and A1 of the synchronous DRAM is connected to A3 of the SH7750
Rev. 4.0, 04/00, page 302 of 850
Bit 1: A6TEH1
0
1
0
1
15
14
—
—
W
W
7
6
—
—
W
W
Bit 0: A6TEH0
0
1
0
1
0
1
0
1
13
12
—
—
W
W
5
4
—
—
W
W
Waits Inserted
0 (Initial value)
1
2
3
6
9
12
15
11
10
—
—
W
W
3
2
—
—
W
W
9
8
—
—
W
W
1
0
—
—
W
W
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