Hitachi SH7751 Hardware Manual page 560

Superh risc engine
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1. Normal data transfer mode (channel 0)

(the data bus available signal) is asserted in response to
signal) from an external device. Two CKIO-synchronous cycles after
external data bus drives the data transfer setting command (DTR command) in synchronization

with
(the transfer request signal). The initial settings are then made in the DMAC channel
0 control register, and the DMA transfer is processed.
2. Normal data transfer mode (except channel 1 to channel 3)
In this mode, the data transfer settings are made in the DMAC from the CPU, and DMA
transfer requests only are performed from the external device.

As in 1 above,
then the DTR command is driven.
The transfer request channel can be specified by means of the two ID bits in the DTR
command.
3. Handshake protocol using the data bus (valid for channel 0 only)
This mode is only valid for channel 0.
After the initial settings have been made in the DMAC channel 0 control register, the DDT
module asserts a data transfer request for the DMAC by setting the DTR command ID = 00,
MD = 00, and SZ
4. Handshake protocol without use of the data bus
The DDT module includes a function for recording the previously asserted request channel. By
using this function, it is possible to assert a transfer request for the channel for which a request
was asserted immediately before, by asserting
request has once been made to the channel for which an initial setting has been made in the
DMAC control register (DTR command and data transfer setting by the CPU in the DMAC).
5. Direct data transfer mode (valid for channel 2 only)
A data transfer request can be asserted for channel 2 by asserting
simultaneously from an external device after the initial settings have been made in the DMAC
channel 2 control register.
is asserted from the external device and the external bus is secured,

101, 110 and driving the DTR command.


only from an external device after a transfer

Rev. 3.0, 04/02, page 521 of 1064
(the data bus request

is asserted, the

and

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