Figure 13.27 Basic Timing For Synchronous Dram Single Write - Hitachi SH7751 Hardware Manual

CKIO
Bank
Precharge-sel
Address
CSn
RD/WR
RAS
CASS
DQMn
D31–D0
(write)
BS
CKE
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.27 Basic Timing for Synchronous DRAM Single Write

Tr Trw Tc1
Row
Row
Row
c1
Tc2 Tc3 Tc4
H/L
c1
Rev. 3.0, 04/02, page 401 of 1064
Trw1 Trw1 Tpc