Figure 23.63 I/O Port Input/Output Timing; Figure 23.64(B) / Input Timing And Output Timing - Hitachi SH7751 Hardware Manual

CKIO
DREQn
DRAKn
CKIO
DBREQ
BAVL
TR
D31 to D0
(READ)
Figure 23.64(b)
Rev. 3.0, 04/02, page 1020 of 1064
CKIO
Ports 31–0
(read)
t
t
PORTD
Ports 31–0
(write)

Figure 23.63 I/O Port Input/Output Timing

t
DRQH
t
DRQS
t
DRAKD
Figure 23.64(a)
t t
DBQS DBQH
t
BAVD
(1): [2CKIO cycle – t
(2): DTR = 1CKIO cycle (= 10 ns: 100 MHz)
(t
DTRS

 
  


/ Input Timing and
t
PORTS PORTH
t
PORTD



/DRAK Timing
t
BAVD
t
TRS
t
DTRS
(2)
(1)
] (= 18 ns: 100 MHz)
DTRS
+ t ) < DTR < 10 ns
DTRH
     
t
DRQH
t
DRQS
t
TRH
t
DTRH
Output Timing