Hardware Itlb Miss Handling - Hitachi SH7750 Programming Manual

MMUCR
31
Entry specification
PTEH
31
VPN
Entry 0 ASID [7:0]
Entry 1 ASID [7:0]
Entry 2 ASID [7:0]
Entry 63 ASID [7:0] VPN [31:10] V
3.5.4

Hardware ITLB Miss Handling

In an instruction access, the SH7750 searches the ITLB. If it cannot find the necessary address
translation information (i.e. in the event of an ITLB miss), the UTLB is searched by hardware, and
if the necessary address translation information is present, it is recorded in the ITLB. This
procedure is known as hardware ITLB miss handling. If the necessary address translation
information is not found in the UTLB search, an instruction TLB miss exception is generated and
processing passes to software.
Rev. 2.0, 03/99, page 46 of 396
26 25 24 23
LRUI — URB
10 9 8 7
— ASID
VPN [31:10] V PPN [28:10]
VPN [31:10] V PPN [28:10]
VPN [31:10] V PPN [28:10]
PPN [28:10] SZ [1:0] SH C PR [1:0]
Figure 3.12 Operation of LDTLB Instruction
18 17 16 15 10 9 8 7
— URC SV
SQMD
PTEL
31 29 28
—
0
PTEA
31
Write
SZ [1:0] SH
SZ [1:0] SH
SZ [1:0] SH
UTLB
3 2 1 0
— TI — AT
10 9 8 7 6 5 4 3 2 1 0
PPN — V SZ PR SZ C D SHWT
4 3 2
—
C PR [1:0] D WT SA [2:0]
C PR [1:0] D WT SA [2:0]
C PR [1:0] D WT SA [2:0]
D WT SA [2:0] TC
0
TC SA
TC
TC
TC