Register Descriptions (Sh7751R); Dma Source Address Registers 0-7 (Sar0-Sar7); Dma Destination Address Registers 0-7 (Dar0-Dar7) - Hitachi SH7751 Hardware Manual

14.7

Register Descriptions (SH7751R)

14.7.1 DMA Source Address Registers 0 – 7 (SAR0 – SAR7)
Bit: 31 30
Initial value: — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14
Initial value: — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DMA source address registers 0–7 (SAR0–SAR7) are 32-bit readable/writable registers that
specify the source address for a DMA transfer. The functions of these registers are the same as on
the SH7751. For more information, see section 14.2.1, DMA Source Address Registers 0–3
(SAR0–SAR3).
14.7.2 DMA Destination Address Registers 0 – 7 (DAR0 – DAR7)
Bit: 31 30
Initial value: — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14
Initial value: — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DMA destination address registers 0–7 (DAR0–DAR7) are 32-bit readable/writable registers that
specify the destination address for a DMA transfer. The functions of these registers are the same
as on the SH7751. For more information, see section 14.2.2, DMA Destination Address Registers
0–3 (DAR0–DAR3).
29 28 27 26
— — — —
13 12 11 10
— — — —
29 28 27 26
— — — —
13 12 11 10
— — — —
25 24 23 22
— — — —
9 8 7 6
— — — —
25 24 23 22
— — — —
9 8 7 6
— — — —
Rev. 3.0, 04/02, page 555 of 1064
21 20 19 18
— — — —
5 4 3 2
— — — —
21 20 19 18
— — — —
5 4 3 2
— — — —
17 16
— —
1 0
— —
17 16
— —
1 0
— —