Hitachi SH7751 Hardware Manual page 317

Bit 7—Periodic Interrupt Flag (PEF): Indicates interrupt generation at the interval specified by
bits PES2–PES0. When this flag is set to 1, a periodic interrupt is generated.
Bit 7: PEF
0
1
Bits 6 to 4—Periodic Interrupt Enable (PES2–PES0): These bits specify the period for periodic
interrupts.
Bit 6: PES2 Bit 5: PES1
0 0
1
1 0
1
Bit 3—Oscillator Enable (RTCEN): Controls the operation of the RTC's crystal oscillator.
Bit 3: RTCEN
0
1
Rev. 3.0, 04/02, page 278 of 1064
Description
Interrupt is not generated at interval specified by bits PES2–PES0
[Clearing condition]
When 0 is written to PEF
Interrupt is generated at interval specified by bits PES2–PES0
[Setting conditions]


Generation of interrupt at interval specified by bits PES2–PES0


When 1 is written to PEF
Bit 4: PES0
0
1
0
1
0
1
0
1
Description
RTC crystal oscillator is halted
RTC crystal oscillator is operated
Description
No periodic interrupt generation
Periodic interrupt generated at 1/256-second intervals
Periodic interrupt generated at 1/64-second intervals
Periodic interrupt generated at 1/16-second intervals
Periodic interrupt generated at 1/4-second intervals
Periodic interrupt generated at 1/2-second intervals
Periodic interrupt generated at 1-second intervals
Periodic interrupt generated at 2-second intervals
(Initial value)
(Initial value)