Figure 22.14 Target Memory Write Cycle In Host Mode (Burst) - Hitachi SH7751 Hardware Manual

PCICLK
AD31–AD0
PAR
C/
–C/
LOCKed
IDSEL
Addr: PCI space address
Dn: nth data
AP: Address parity
DPn: nth data parity
Com: Command
BEn: nth data byte enable

Figure 22.14 Target Memory Write Cycle in Host Mode (Burst)

Addr
D0
AP
Com BE0
D1
DP0
BE1
Rev. 3.0, 04/02, page 907 of 1064
Dn
DP DPn
n-1
BEn
Disconnect