Figure 13.40 Basic Timing Of A Burst Write To Synchronous Dram - Hitachi SH7751 Hardware Manual

In a cycle of access to synchronous DRAM, the
beginning of a bus cycle. Data are accessed in the following sequence: in the fill operation for
a cache miss, the data between the 32-bit boundaries that include the missed data are first read;
after that, the data between 32-byte boundaries that include the missed data are read in a
wraparound way.


Burst Write
Figure 13.40 is the timing chart for a burst-write operation with a burst length of 8. In this LSI,
a burst write takes place when a copy-back of the cache or a 32-byte transfer of data by the
DMAC takes place. In a burst-write operation, a WRITA command that include auto
precharging, is issued during the Tc1 cycle that follows the Tr cycle in which the ACTV
command is output. During the write cycle, the data to be written is output along with the write
command. With a write command that includes an auto precharge, precharging is of the
relevant bank of the synchronous DRAM and takes place on completion of the write
command, so no new command that accesses the same bank can be issued until precharging
has been completed. For this reason, the Trwl cycles are added as a period of waiting for
precharging to start after the write command has been issued. This is additional to the
precharge-waiting cycle as used in read access. The Trwl cycles delay the issuing of new
commands to the same bank. The setting of the TRWL2 to TRWL0 bits of MCR selects the
number of Trwl cycles. The data between 32-byte boundaries are written in a wraparound way.
Tr
CKIO
Bank
Precharge-sel
Address
RD/
DQMn
D31–D0
(write)
CKE
DACKn
(SA: IO → memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.40 Basic Timing of a Burst Write to Synchronous DRAM

Rev. 3.0, 04/02, page 418 of 1064
Trw Tc1 Tc2 Tc3
Row
Row H/L
Row c1
c1 c2

signal is asserted for one clock cycle at the
Tc4 Tc5 Tc6 Tc7
c3 c4 c5 c6
Tc8 Trw1 Trw1 Tpc
c7 c8