Register Configuration; Caution; Table 3.1 Mmu Registers - Hitachi SH7751 Hardware Manual

3.1.3

Register Configuration

The MMU registers are shown in table 3.1.
Table 3.1 MMU Registers
Name
Page table entry high
register
Page table entry low
register
Page table entry
assistance register
Translation table base
register
TLB exception address
register
MMU control register
Notes: *1 The initial value is the value after a power-on reset or manual reset.
*2 P4 address is the address when using the virtual/physical address space P4 area. The
area 7 address is the address used when making an access from physical address
space area 7 using the TLB.
3.1.4

Caution

Operation is not guaranteed if an area designated as a reserved area in this manual is accessed.
Rev. 3.0, 04/02, page 54 of 1064
Abbrevia- Initial
tion R/W Value*
PTEH R/W Undefined
PTEL R/W Undefined
PTEA R/W Undefined
TTB R/W Undefined
TEA R/W Undefined
MMUCR R/W H'0000 0000 H'FF00 0010 H'1F00 0010 32
P4
1 2
Address*
H'FF00 0000 H'1F00 0000 32
H'FF00 0004 H'1F00 0004 32
H'FF00 0034 H'1F00 0034 32
H'FF00 0008 H'1F00 0008 32
H'FF00 000C H'1F00 000C 32
Area 7 Access
2
Address* Size