H-Udi Reset; H-Udi Interrupt; Figure 21.3 H-Udi Reset - Hitachi SH7751 Hardware Manual

21.3.2

H-UDI Reset

A power-on reset is effected by an SDIR command. A reset is effected by sending a H-UDI reset
assert command, and then sending a H-UDI reset negate command, from the H-UDI pin (see
figure 21.3). The interval required between the H-UDI reset assert command and the H-UDI reset
negate command is the same as the length of time the reset pin is held low in order to effect a
power-on reset.
H-UDI pin
Chip internal reset
CPU state
21.3.3

H-UDI Interrupt

The H-UDI interrupt function generates an interrupt by setting a command value in SDIR from the
H-UDI. The H-UDI interrupt is of general exception/interrupt operation type, with a branch to an
address based on VBR and return effected by means of an RTE instruction. The exception code
stored in control register INTEVT in this case is H'600. The priority of the H-UDI interrupt can be
controlled with bits 3 to 0 of control register IPRC.
The H-UDI interrupt request signal is asserted when, after the command is set (Update-IR), the
INTREQ bit of the SDINT register is set to 1. The interrupt request signal is not negated until 0 is
written to the INTREQ bit by software, and there is therefore no risk of the interrupt request being
unexpectedly missed. While the H-UDI interrupt command is set in SDIR, the SDINT register is
connected between TDI and TDO.
H-UDI
reset assert
Normal

Figure 21.3 H-UDI Reset

H-UDI
reset negate
Reset Reset processing
Rev. 3.0, 04/02, page 799 of 1064