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Table 23.31 PCIC Signal Timing (in PCIREQ/PCIGNT Non-Port Mode) (2)
HD6417751BP167, HD6417751F167: V
C
= 30 pF
L
HD6417751BP167I, HD6417751F167I: V
C
= 30 pF
L
HD6417751F133: V
DDQ
Pin
Item
PCICLK
Clock cycle
Clock pulse width (high)
Clock pulse width (low)
Clock rise time
Clock fall time
Output data delay time
IDSEL
Input hold time
Input setup time
AD31–AD0
Output data delay time
C/
–C/
Tri-state drive delay time
PAR
Tri-state high-impedance
delay time
Input hold time
Input setup time
/
Output data delay time
Tri-state drive delay time
/
Tri-state high-impedance
MD9
delay time
/
Input hold time
MD10
Input setup time
/
/
–
Tri-state drive delay time
Tri-state high-impedance
delay time
Rev. 3.0, 04/02, page 1024 of 1064
= 3.0 to 3.6 V, V
DDQ
DDQ
= 3.0 to 3.6 V, V
= 1.5 V, Ta = –20 to 75
DD
Symbol
t
PCICYC
t
PCIHIGH
t
PCILOW
t
PCIr
t
PCIf
t
PCIVAL
t
PCIH
t
PCISU
t
PCIVAL
t
PCION
t
PCIOFF
t
PCIH
t
PCISU
t
PCIVAL
t
PCION
t
PCIOFF
t
PCIH
t
PCISU
t
PCION
t
PCIOFF
= 1.8 V, T
DD
= 3.0 to 3.6 V, V
= 1.8 V, Ta = –40 to 85
DD
33 MHz
Min
Max
30
—
11
—
11
—
—
4
—
4
—
10
1
—
3
—
—
10
—
10
—
12
1
—
3
—
—
10
—
10
—
12
1
—
3
—
—
10
—
12
= –20 to 75
C,
a
C, C
= 30 pF
L
66 MHz
Min
Max
Unit
15
30
ns
6
—
ns
6
—
ns
—
1.5
ns
—
1.5
ns
—
10
ns
1
—
ns
3
—
ns
—
10
ns
—
10
ns
—
12
ns
1
—
ns
3
—
ns
—
10
ns
—
10
ns
12
ns
1
—
ns
3
—
ns
—
10
ns
—
12
ns
C,
Figure
23.70
23.70
23.70
23.70
23.70
23.71
23.72
23.72
23.71
23.71
23.71
23.72
23.72
23.71
23.71
23.71
23.72
23.72
23.71
23.71
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