Figure 13.54 Mpx Interface Timing 3 (Single Write Cycle, Anw = 0, No External Wait) - Hitachi SH7751 Hardware Manual

Tm1 Tmd1
CKIO
/
D31–D0
A D0
RD/
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.54 MPX Interface Timing 3 (Single Write Cycle, AnW = 0, No External Wait)

Rev. 3.0, 04/02, page 437 of 1064