Endian Control For Local Bus; Endian Control In Dma Transfers; Figure 22.19 Endian Control For Local Bus - Hitachi SH7751 Hardware Manual

22.4.2

Endian Control for Local Bus

Big and little endians are supported on the local bus, determined at power-on reset by the external
endian specification pin (MD5). Therefore, when transferring data between the local bus and the
PCI bus, when the local bus is set for big endian, big/little endian conversion is therefore required.
Figure 22.19 shows the block diagram of the local bus endian control. An endian conversion
circuit is provided between the local bus and the FIFO. For details of the endian control, refer to
section 22.4.3, Endian Control in DMA Transfers, and section 22.4.4, Endian Control in Target
Transfers (Memory Read/Memory Write).
Local bus
32 bits
32 bits
Big/little endian
22.4.3

Endian Control in DMA Transfers

Although only the longword access size is supported in DMA transfers (see table 22.11), the
endian conversion mode can be selected from the following four types depending on whether the
longword data consists of four byte data units or two word data units.
The conversion mode can be switched by the setting of bits 10 and 9 (ALNMD) of the DMA
control registers (PCIDCR0 to 3) for PCI.
1. Byte data boundary mode: Big/little endian conversion is performed on the assumption that all
data is on a byte boundary. (ALNMD = b'00)
2. Word/longword (W/LW) boundary mode 1: Longword data is transferred as byte data x 4.
(ALNMD = b'01)
3. Word/longword (W/LW) boundary mode 2: Longword data is transferred as word data x 2.
(ALNMD = b'10)
4. Word/longword (W/LW) boundary mode 3: Longword data is transferred as longword data x
1. (ALNMD = b'11)
Rev. 3.0, 04/02, page 912 of 1064
Big/little →
little
Little →
big/little
B, W, LW

Figure 22.19 Endian Control for Local Bus

FIFO
LW
DMA
LW
Target RD
FIFO
LW
DMA
Targer WT
PCI bus
32 bits
32 bits
Little endian