Oc Index Mode; Coherency Between Cache And External Memory; Prefetch Operation; Instruction Cache (Ic) - Hitachi SH7751 Hardware Manual

Superh risc engine
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4.3.7

OC Index Mode

Setting CCR.OIX to 1 enables OC indexing to be performed using bit [25] of the effective
address. This is called OC index mode. In normal mode, with CCR.OIX cleared to 0, OC indexing
is performed using bits [13:5] of the effective address. Using index mode allows the OC to be
handled as two areas by means of effective address bit [25], providing efficient use of the cache.
Note that in the SH7751R, RAM mode cannot be used when OC index mode is used.
4.3.8

Coherency between Cache and External Memory

Coherency between cache and external memory should be assured by software. In the SH7751
Series, the following four new instructions are supported for cache operations. Details of these
instructions are given in the Programming Manual.
Invalidate instruction:
Purge instruction:
Write-back instruction:
Allocate instruction:
4.3.9

Prefetch Operation

The SH7751 Series supports a prefetch instruction to reduce the cache fill penalty incurred as the
result of a cache miss. If it is known that a cache miss will result from a read or write operation, it
is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a
cache miss due to the read or write operation, and so improve software performance. If a prefetch
instruction is executed for data already held in the cache, or if the prefetch address results in a
UTLB miss or a protection violation, the result is no operation, and an exception is not generated.
Details of the prefetch instruction are given in the Programming Manual.
Prefetch instruction:
4.4

Instruction Cache (IC)

4.4.1

Configuration

The instruction cache consists of 256 cache lines, each composed of a 19-bit tag, V bit, and 32-
byte data (16 instructions). The instruction cache in the SH7751R adopts the 2-way set-associative
method, and each way consists of 256 cache lines.
OCBI @Rn
OCBP @Rn
OCBWB @Rn
MOVCA.L R0,@Rn
PREF @Rn
Cache invalidation (no write-back)
Cache invalidation (with write-back)
Cache write-back
Cache allocation
Rev. 3.0, 04/02, page 99 of 1064

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