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Table 8.2
Parallel-Executability
1st
MT
Instruction
EX
BR
LS
FE
CO
O: Can be executed in parallel
X: Cannot be executed in parallel
8.3
Execution Cycles and Pipeline Stalling
There are three basic clocks in this processor: the I-clock, B-clock, and P-clock. Each hardware
unit operates on one of these clocks, as follows:
I-clock: CPU, FPU, MMU, caches
B-clock: External bus controller
P-clock: Peripheral units
The frequency ratios of the three clocks are determined with the frequency control register
(FRQCR). In this section, machine cycles are based on the I-clock unless otherwise specified. For
details of FRQCR, see section 10, Clock Oscillation Circuits.
Instruction execution cycles are summarized in table 8.3. Penalty cycles due to a pipeline stall or
freeze are not considered in this table.
Issue rate: Interval between the issue of an instruction and that of the next instruction
Latency: Interval between the issue of an instruction and the generation of its result
(completion)
Instruction execution pattern (see figure 8.2)
Lock stage: Locked pipeline stages(see table 8.3)
Lock start: Interval between the issue of an instruction and the start of locking (see table 8.3)
Lock cycle: Lock time (see table 8.3)
Rev. 3.0, 04/02, page 198 of 1064
2nd Instruction
MT
EX
BR
O
O
O
O
X
O
O
O
X
O
O
O
O
O
O
X
X
X
LS
FE
CO
O
O
X
O
O
X
O
O
X
X
O
X
O
X
X
X
X
X
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