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Table 23.32 PCIC Signal Timing
(With PCIREQ/PCIGNT Port Settings in Non-Host Mode) (1)
HD6417751RBP240, HD6417751RBP200, HD6417751RF240, HD6417751RF200:
V
= 3.0 to 3.6 V, V
DDQ
Pin
/MD9
/MD10
–
Table 23.33 PCIC Signal Timing
(With PCIREQ/PCIGNT Port Settings in Non-Host Mode) (2)
HD6417751BP167, HD6417751F167: V
C
= 30 pF
L
HD6417751BP167I, HD6417751F167I: V
C
= 30 pF
L
Pin
/MD9
/MD10
–
Rev. 3.0, 04/02, page 1026 of 1064
PCICLK
0.4V
Input
Figure 23.72 Output Signal Timing
= 1.5 V, T
= –20 to 75
DD
a
Item
Output data delay
time
Input hold time
Input setup time
Output data delay
time
DDQ
DDQ
Item
Output data delay
time
Input hold time
Input setup time
Output data delay
time
0.4V
t
t
PCISU
PCIH
DDQ
C, C
= 30 pF
L
Symbol
Min
t
—
PCIPORTD
t
1.5
PCIPORTH
t
3.5
PCIPORTS
t
—
PCIPORTD
= 3.0 to 3.6 V, V
= 1.8 V, Ta = –20 to 75
DD
= 3.0 to 3.6 V, V
DD
Symbol
Min
t
—
PCIPORTD
t
1.5
PCIPORTH
t
3.5
PCIPORTS
t
—
PCIPORTD
DDQ
0.4V
DDQ
Max
Unit
Figure
10
ns
23.73
—
ns
23.73
—
ns
23.73
10
ns
23.73
= 1.8 V, Ta = –40 to 85
Max
Unit
Figure
10
ns
23.73
—
ns
23.73
—
ns
23.73
10
ns
23.73
C,
C,
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