Table 7.5 Logic Operation Instructions - Hitachi SH7751 Hardware Manual

Table 7.5 Logic Operation Instructions
Instruction
AND Rm,Rn
AND #imm,R0
AND.B #imm,@(R0,GBR) (R0 + GBR) & imm
NOT Rm,Rn
OR Rm,Rn
OR #imm,R0
OR.B #imm,@(R0,GBR) (R0 + GBR) | imm
TAS.B @Rn
TST Rm,Rn
TST #imm,R0
#imm,@(R0,GBR) (R0 + GBR) & imm; when result
TST.B
XOR Rm,Rn
XOR #imm,R0
XOR.B #imm,@(R0,GBR) (R0 + GBR)
Rev. 3.0, 04/02, page 178 of 1064
Operation

Rn & Rm Rn

R0 & imm R0

(R0 +
GBR)

~Rm Rn

Rn | Rm Rn

R0 | imm R0

(R0 +
GBR)

When (Rn) = 0, 1 T

Otherwise, 0 T

In both cases, 1 MSB of (Rn)
Rn & Rm; when result = 0,

1 T

Otherwise, 0 T
R0 & imm; when result = 0,

1 T

Otherwise, 0 T

= 0, 1 T

Otherwise, 0 T


Rn Rm Rn


R0 imm R0


imm (R0 +
GBR)
Instruction Code
0010nnnnmmmm1001 —
11001001iiiiiiii —
11001101iiiiiiii —
0110nnnnmmmm0111 —
0010nnnnmmmm1011 —
11001011iiiiiiii —
11001111iiiiiiii —
0100nnnn00011011 —
0010nnnnmmmm1000 —
11001000iiiiiiii —
11001100iiiiiiii —
0010nnnnmmmm1010 —
11001010iiiiiiii —
11001110iiiiiiii —
Privileged T Bit
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—
—
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Test result
Test result
Test result
Test result
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