Table of Contents
Advertisement
Since channel 1 is in burst mode (in the case of edge sensing) regardless of whether fixed mode or
round robin mode is set for the priority order, the bus is not released to the CPU until channel 1
transfer ends.
CPU
DMAC CH1
CPU
DMAC channel 1
burst mode
Priority system: Round robin mode
Channel 0:
Channel 1:
Figure 14.11 Bus Handling with Two DMAC Channels Operating
Note: When channel 1 is in level-sensing burst mode with the settings shown in figure 14.11, the
bus is passed to the CPU during a break in requests.
14.3.5
Number of Bus Cycle States and
Number of States in Bus Cycle: The number of states in the bus cycle when the DMAC is the
bus master is controlled by the bus state controller (BSC) just as it is when the CPU is the bus
master. See section 13, Bus State Controller (BSC), for details.
DREQ Pin Sampling Timing: In external request mode, the
edge of CKIO clock pulses. When
DMA transfer executed after four CKIO cycles at the earliest.
With
falling edge detection, as the signal passes via an asynchronous circuit the DMAC
recognizes
two cycles (CKIO) later (one cycle (CKIO) later in the case of low level
detection).
The second and subsequent
the first DMAC transfer bus cycle (in the case of single address mode).
DRAK is output for one cycle only, once each time
mode or
detection method. In the case of burst mode edge detection,
the first cycle only, and so DRAK is output in the first cycle only .
Operation: Figures 14.12 to 14.22 show the timing in each mode.
Rev. 3.0, 04/02, page 502 of 1064
DMAC CH1
DMAC CH0
CH0
DMAC channel 0 and
channel 1 round robin
mode
Cycle steal mode
Burst mode (edge-sensing)
input is detected, a DMAC bus cycle is generated and
sampling operations are performed one cycle after the start of
DMAC CH1
DMAC CH0
CH1
CH0
Pin Sampling Timing
is detected, regardless of the transfer
DMAC CH1
DMAC CH1
DMAC channel 1
burst mode
pin is sampled at the rising
is sampled in
CPU
CPU
Advertisement
Table of Contents
