Section 8 Pipelining; Pipelines - Hitachi SH7751 Hardware Manual

Section 8 Pipelining

The SH7751 Series is a 2-ILP (instruction-level-parallelism) superscalar pipelining
microprocessor. Instruction execution is pipelined, and two instructions can be executed in
parallel. The execution cycles depend on the implementation of a processor. Definitions in this
section may not be applicable to SH-4 Series models other than the SH7751 Series.
8.1

Pipelines

Figure 8.1 shows the basic pipelines. Normally, a pipeline consists of five or six stages: instruction
fetch (I), decode and register read (D), execution (EX/SX/F0/F1/F2/F3), data access (NA/MA),
and write-back (S/FS). An instruction is executed as a combination of basic pipelines. Figure 8.2
shows the instruction execution patterns.
Rev. 3.0, 04/02, page 187 of 1064