Figure 23.47 Dram Bus Cycle: Dram Cas-Before-Ras Refresh (Tras [2:0] = 000, Trc [2:0] = 001) - Hitachi SH7751 Hardware Manual

TRr1
CKIO
t
AD
A25–A0
t
CSD
t
RWD
RD/
t
RASD
t
CASD1
t
WDD
D31–D0
(write)
t
DACD
DACKn
(SA: IO ← memory)
t
DACD
DACKn
(SA: IO → memory)
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.47 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
TRr2 TRr3 TRr4
t
RASD
t
CASD1
(TRAS [2:0] = 000, TRC [2:0] = 001)
TRr5 Trc Trc
t
RASD
t
CASD1
Rev. 3.0, 04/02, page 1003 of 1064
Trc