Hitachi SH7751 Hardware Manual page 162

Table 5.2 Exceptions (cont)
Exception Execution
Category Mode
Interrupt Completion
type
Exception
Nonmaskable interrupt
External IRL3–IRL0
interrupts
Peripheral TMU0
module
TMU1
interrupt
TMU2
(module/
source)
TMU3
TMU4
RTC
SCI
WDT
REF
Priority Priority
Level Order
3 —
0 4 *2
1
2
3
4
5
6
7
8
9
A
B
C
D
E
TUNI0 4 *2
TUNI1
TUNI2
TICPI2
TUNI3
TUNI4
ATI
PRI
CUI
ERI
RXI
TXI
TEI
ITI
RCMI
ROVI
Vector
Address Offset
(VBR) H'600
(VBR) H'600
(VBR) H'600
Rev. 3.0, 04/02, page 123 of 1064
Exception
Code
H'1C0
H'200
H'220
H'240
H'260
H'280
H'2A0
H'2C0
H'2E0
H'300
H'320
H'340
H'360
H'380
H'3A0
H'3C0
H'400
H'420
H'440
H'460
H'B00
H'B80
H'480
H'4A0
H'4C0
H'4E0
H'500
H'520
H'540
H'560
H'580
H'5A0