Hitachi SH7751 Hardware Manual page 436


In a synchronous DRAM cycle, the signal is asserted for one cycle at the beginning of each
data transfer cycle that is in response to a READ or READA command. Data are accessed in the
following sequence: in the fill operation for a cache miss, the data between 64-bit boundaries that
include the missing data are first read by the initial READ command; after that, the data between
16-bit boundaries data that include the missing data are read in a wraparound way. The
subsequently issued READA command reads the 16 bytes of data, which is the remainder of the
data between 32-byte boundaries.
Single Read: With the SH7751 Series, as synchronous DRAM is set to burst read/burst write
mode, read data output continues after the required data has been read. To prevent data collisions,
after the required data is read in Td1, empty read cycles Td2 to Td4 are performed, and the

SH7751 Series waits for the end of the synchronous DRAM operation. The signal is asserted
only in Td1.
There are 4 burst transfers in a read. In cache-through and other DMA read cycles, of cycles Td1
to Td4.
Since such empty cycles increase the memory access time, and tend to reduce program execution
speed and DMA transfer speed, it is important both to avoid unnecessary cache-through area
accesses, and to use a data structure that will allow data to be placed at a 32-byte boundary, and to
be transferred in 32-byte units, when carrying out DMA transfer with synchronous DRAM
specified as the source.
Rev. 3.0, 04/02, page 397 of 1064