Pci Control Register (Pcicr) - Hitachi SH7751 Hardware Manual

22.2.17 PCI Control Register (PCICR)

Bit: 31
—
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
Bit: 23
—
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
Bit: 15
—
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
Bit: 7
PCIPUP
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R/W
Note: * The value of the external pin is sampled in a power-on reset by means of the
The PCI control register (PCICR) is a 32-bit register that monitors the status of the mode pin at
initialization and controls the basic operation of the PCIC. Bits 5 (MD10) and 4 (MD9) are read-
only bits from the PP bus. Other bits are read/write bits. Bits 9 (TRDSGL) and 8 (BYTESWAP)
are read/write bits from the PCI bus. Other bits are read-only.
In PCIC host operation, a software reset can be applied to the PCI bus by means of bit 1
(RSTCTL) of PCICR. When a software reset is executed, the
internal state of the PCIC is initialized.
The PCICR register is initialized at a power-on reset to H'000000*0 (bits 7 and 6 are initialized to
B'00, and bits 5 and 4 sample the value of mode pins 9 and 10). At a software reset, bit 1
(RSTCTL) is not initialized. All other bits are initialized in the same way as at a software reset.
30 29
— —
0 0
R R
R R
22 21
— —
0 0
R R
R R
14 13
— —
0 0
R R
R R
6 5
BMABT MD10
0 0/1*
R R
R/W R
28 27
— —
0 0
R R
R R
20 19
— —
0 0
R R
R R
12 11
— —
0 0
R R
R R
4 3
MD9 SERR INTA
0/1* 0
R R
R R/W
 
Rev. 3.0, 04/02, page 839 of 1064
26 25
— —
0 0
R R
R R
18 17
— —
0 0
R R
R R
10 9
— TRDSGL
BYTESWAP
0 0
R R/W R/W
R R/W R/W
2 1
RSTCTL CFINIT
0 0
R R
R/W R/W R/W


pin is asserted and the
24
—
0
R
R
16
—
0
R
R
8
0
0
0
R
pin.