Clock Stop Register 00 (Clkstp00) - Hitachi SH7751 Hardware Manual

Bit 0—Module Stop 5 (MSTP5): Specifies stopping of the clock supply to the user break
controller (UBC) among the on-chip peripheral modules. See section 20.6, User Break Controller
Stop Function for how to set the clock supply.
Bit 0: MSTP5
0
1
9.2.5

Clock Stop Register 00 (CLKSTP00)

Clock stop register 00 (CLKSTP00) is a 32-bit readable/writable register that controls the
operating clock for peripheral modules.
The clock supply is restarted by writing 1 to the corresponding bit in the CLKSTPCLR00 register.
Writing 0 to CLKSTP00 will not change the bit value.
CLKSTP00 is initialized to H'00000000 by a reset. It is not initialized in standby mode.
Bit: 31
—
Initial value: 0
R/W: R
Bit: 7
—
Initial value: 0
R/W: R
Bits 31 to 3—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 2—Clock Stop 2 (CSTP2): Specifies stopping of the peripheral clock supply to the PCI bus
controller (PCIC). For details see section 22, PCI Controller (PCIC).
Bit 2: CSTP2
0
1
Rev. 3.0, 04/02, page 222 of 1064
Description
UBC operating
Clock supply to UBC stopped
30 29
— —
0 0
R R
6 5
— —
0 0
R R
Description
Peripheral clock is supplied to PCIC
Peripheral clock supply to PCIC is stopped
... 11 10
... —
... 0
... R
4 3
— — CSTP2
0 0
R R R/W
(Initial value)
9
— — —
0 0
R R
2 1
CSTP1 CSTP0
0 0
R/W R/W
(Initial value)
8
0
R
0
0