Hitachi SH7751 Hardware Manual page 691

SCFCR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in
standby mode or in the module standby state.
Bits 15 to 11—Reserved: These bits are always read as 0, and should only be written with 0.



Bits 10, 9 and 8—
output the high level to the
FIFO data register (SCFRDR2) exceeds the trigger number, as shown in the table below.
Bit 10: RSTRG2 Bit 9: RSTRG1
0 0
1
1 0
1
Bits 7 and 6—Receive FIFO Data Number Trigger (RTRG1, RTRG0): These bits are used to
set the number of receive data bytes that sets the receive data full (RDF) flag in the serial status
register (SCFSR2).
The RDF flag is set when the number of receive data bytes in SCFRDR2 is equal to or greater than
the trigger set number shown in the following table.
Bit 7: RTRG1 Bit 6: RTRG0
0 0
1
1 0
1
Rev. 3.0, 04/02, page 652 of 1064
Output Active Trigger (RSTRG2, RSTG1, and RSTG0): These bits


signal when the number of received data stored in the receive
Bit 8: RSTRG0
0
1
0
1
0
1
0
1
Receive Trigger Number
1
4
8
14
 
Output Active Trigger
15
1
4
6
8
10
12
14
(Initial value)
(Initial value)