Dma Operation Register (Dmaor) - Hitachi SH7751 Hardware Manual

14.2.5

DMA Operation Register (DMAOR)

Bit: 31
—
Initial value: 0
R/W: R
Bit: 23
—
Initial value: 0
R/W: R
Bit: 15
DDT
Initial value: 0
R/W: R/W
Bit: 7
—
Initial value: 0
R/W: R
Note: The AE and NMIF bits can only be written with 0 after being read as 1, to clear the flags.
DMAOR is a 32-bit readable/writable register that specifies the DMAC transfer mode.
DMAOR is initialized to H'00000000 by a power-on or manual reset. They retain their values in
standby mode and deep sleep mode.
Bits 31 to 16—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 15—On-Demand Data Transfer (DDT): Specifies on-demand data transfer mode.
Bit 15: DDT
0
1

Note: (DRAK0) is an active-high output in normal DMA mode. When the DDT bit is set to 1,

the pin function is enabled and this pin becomes an active-low output.
30 29
— —
0 0
R R
22 21
— —
0 0
R R
14 13
— —
0 0
R R
6 5
— —
0 0
R R
Description
Normal DMA mode
On-demand data transfer mode
28 27
— —
0 0
R R
20 19
— —
0 0
R R
12 11
— —
0 0
R R
4 3
— — AE
0 0
R R R/(W)
Rev. 3.0, 04/02, page 481 of 1064
26 25 24
— —
0 0
R R
18 17 16
— —
0 0
R R
10 9
— PR1 PR0
0 0
R R/W R/W
2 1
NMIF DME
0 0
R/(W) R/W
(Initial value)
—
0
R
—
0
R
8
0
0
0