Pci Configuration Register 3 (Pciconf3) - Hitachi SH7751 Hardware Manual

22.2.4

PCI Configuration Register 3 (PCICONF3)

Bit: 31
BIST7
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
Bit: 23
HEAD7
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
Bit: 15
LAT7
Initial value: 0
PCI-R/W: R/W
PP Bus-R/W: R/W
Bit: 7
CACHE7 CACHE6 CACHE5 CACHE4 CACHE3 CACHE2 CACHE1 CACHE0
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
The PCI configuration register 3 (PCICONF3) is a 32-bit read/partial-write register that includes
the BIST function, header type, latency timer, and cache line size PCI configuration registers
stipulated in the PCI local bus specification. The BIST function is read from bits 31 to 24, the
header type from bits 23 to 16, the cache line size from bits 7 to 0. The guaranteed time for the
PCIC to occupy the PCI bus when the PCIC is master is set in bits 15-8 (latency timer).
Bits 15 to 8 can be written to. Other bits are fixed in hardware.
The PCICONF3 register is initialized to H'00000000 at a power-on reset and software reset.
30 29
BIST6 BIST5
0 0
R R
R R
22 21
HEAD6 HEAD5 HEAD4
0 0
R R
R R
14 13
LAT6 LAT5
0 0
R/W R/W
R/W R/W
6 5
0 0
R R
R R
28 27
BIST4 BIST3 BIST2
0 0
R R
R R
20 19
HEAD3 HEAD2
0 0
R R
R R
12 11
LAT4 LAT3
0 0
R/W R/W
R/W R/W
4 3
0 0
R R
R R
Rev. 3.0, 04/02, page 819 of 1064
26 25
BIST1 BIST0
0 0
R R
R R
18 17
HEAD1 HEAD0
0 0
R R
R R
10 9
LAT2 LAT1
0 0
R/W R/W
R/W R/W
2 1
0 0
R R
R R
24
0
R
R
16
0
R
R
8
LAT0
0
R/W
R/W
0
0
R
R