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13.1.5
Overview of Areas
Space Divisions: The architecture of the SH7751 Series provides a 32-bit virtual address space.
The virtual address space is divided into five areas according to the upper address value. External
memory space comprises a 29-bit address space, divided into eight areas.
The virtual address can be allocated to any external address by means of the memory management
unit (MMU). Details are given in section 3, Memory Management Unit (MMU). This section
describes the areas into which the external address is divided.
With the SH7751 Series, various kinds of memory or PC cards can be connected to the seven
areas of external address as shown in table 13.3, and chip select signals (
are output for each of these areas.
area 6. When DRAM or synchronous DRAM is connected to area 2 or 3, signals such as
, RD/
, and DQM are also asserted. When the PCMCIA interface is selected for area 5 or
6,
,
is asserted in addition to
H'0000 0000
P0 and
U0 areas
H'8000 0000
P1 area
H'A000 0000
P2 area
H'C000 0000
P3 area
H'E000 0000
Store queue area
H'E400 0000
P4 area
H'FFFF FFFF
Physical address
space
(MMU off)
Notes: 1. When the MMU is off (MMUCR.AT = 0), the top 3 bits of the 32-bit address are ignored, and
memory is mapped onto a fixed 29-bit external address.
2. When the MMU is on (MMUCR.AT = 1), the P0, U0, P3, and store queue areas can be
mapped onto any external space using the TLB.
For details, see section 3, Memory Management Unit (MMU).
Figure 13.2 Correspondence between Virtual Address Space and External Memory Space
is asserted when accessing area 0, and
,
for the byte to be accessed.
256
P0 and
U0 areas
P1 area
P2 area
P3 area
Store queue area
P4 area
Virtual address
space
(MMU on)
–
,
when accessing
Area 0 (
)
H'0000 0000
Area 1 (
)
H'0400 0000
Area 2 (
)
H'0800 0000
Area 3 (
)
H'0C00 0000
Area 4 (
)
H'1000 0000
H'1400 0000
Area 5 (
)
H'1800 0000
Area 6 (
)
H'1C00 0000
Area 7 (reserved area)
H'1FFF FFFF
External memory
space
Rev. 3.0, 04/02, page 311 of 1064
,
)
,
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