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Bit:
15
Initial value:
—
R/W:
W
Bit:
7
Initial value:
—
R/W:
W
Since the address bus, not the data bus, is used to write to the synchronous DRAM mode register,
if the value to be set is "X" and the SDMR register address is "Y", value "X" is written to the
synchronous DRAM mode register by performing a write to address X + Y. When the
synchronous DRAM bus width is set to 32 bits, as A0 of the synchronous DRAM is connected to
A2 of the SH7751 Series, and A1 of the synchronous DRAM is connected to A3 of the SH7751
Series, the value actually written to the synchronous DRAM is the value of "X" shifted 2 bits to
the right.
For example, to write H'0230 to the area 2 SDMR register, arbitrary data is written to address
H'FF900000 (address "Y") + H'08C0 (value "X") (= H'FF9008C0). As a result, H'0230 is written
to the SDMR register. The range of value "X" is H'0000 to H'0FFC.
Similarly, to write H'0230 to the area 3 SDMR register, arbitrary data is written to address
H'FF940000 (address "Y") + H'08C0 (value "X") (= H'FF9408C0). As a result, H'0230 is written
to the SDMR register. The range of value "X" is H'0000 to H'0FFC.
The lower 16 bits of the address are set in the synchronous DRAM mode register.
The burst length is 4 and 8*. Setting to SDMR writes into the following addresses in byte size.
Note: * SH7751R only
Bus Width
32
4
32
8*
14
13
—
—
W
W
6
5
—
—
W
W
CAS Latency
1
2
3
1
2
3
12
11
—
—
W
W
4
3
—
—
W
W
Area 2
H'FF900048
H'FF900088
H'FF9000C8
H'FF90004C
H'FF90008C
H'FF9000CC
Rev. 3.0, 04/02, page 353 of 1064
10
9
—
—
W
W
2
1
—
—
W
W
Area 3
H'FF940048
H'FF940088
H'FF9400C8
H'FF94004C
H'FF94008C
H'FF9400CC
8
—
W
0
—
W
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