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insertion specified by WCR2. AnTED2–AnTED0 can be set to a value from 0 to 15, enabling the
address,
,
,
, and
setup times with respect to the
and
signals to be
secured. AnTEH2–AnTEH0 can also be set to a value from 0 to 15, enabling the address,
,
,
, and
data hold times with respect to the
and
signals to be secured.
Wait cycles between cycles are set with bits A5IW2–A5IW0 and A6IW2–A6IW0 in wait control
register 1 (WCR1). The inter-cycle write cycles selected depend only on the area accessed (area 5
or 6): when area 5 is accessed, bits A5IW2–A5IW0 are selected, and when area 6 is accessed, bits
A6IW2–A6IW0 are selected.
In 32-byte transfer, a total of 32 bytes are transferred consecutively according to the set bus width.
The first access is performed on the data for which there was an access request, and the remaining
accesses are performed in wraparound mode on the data at the 32-byte boundary. The bus is not
released during this operation.
Rev. 3.0, 04/02, page 423 of 1064
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