Figure 23.45 Dram Burst Bus Cycle: Ras Down Mode State (Fast Page Mode, Rcd [1:0] = 00, Anw [2:0] = 000) - Hitachi SH7751 Hardware Manual

Tpc
CKIO
Address
RD/
D31–D0
(read)
D31–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.45 DRAM Burst Bus Cycle: RAS Down Mode State
Tr1 Tr2 Tc1
t
t
AD
AD
Row
t
CSD
t
RWD
t t
RASD RASD
t t
CASD1 CASD1
t
t t
WDD WDD
d1
t
BSD
t t
DACD DACD
t t
DACD DACD
(Fast Page Mode, RCD [1:0] = 00, AnW [2:0] = 000)
Tc2 Tc1 Tc2
c1 c2
t
CASD1
t
RDS RDH
d1 d2
t
WDD
d2
t
BSD
t
DACD
t
DACD
Rev. 3.0, 04/02, page 1001 of 1064
Tc1 Tc2 Tc1 Tc2
c8
t
CASD1
t
RDS
d8
t
AD
t
CSD
t
RWD
t
CASD1
t
RDH
d8
t
WDD