Figure 13.11 Sram Interface Wait State Timing (Wait State Insertion By Signal) - Hitachi SH7751 Hardware Manual

When software wait insertion is specified by WCR2, the external wait input


sampled. signal sampling is shown in figure 13.11. A single-cycle wait is specified as a
software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore,


the signal has no effect if asserted in the T1 cycle or the first Tw cycle. The
sampled on the rising edge of the clock.
CKIO
A25–A0
RD/
(read)
D31–D0
(read)
(write)
D31–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.
Figure 13.11 SRAM Interface Wait State Timing (Wait State Insertion by
Rev. 3.0, 04/02, page 376 of 1064
T1 Tw


Twe T2
signal is also


signal is



Signal)