Figure 13.18 Burst Access Timing In Dram Edo Mode - Hitachi SH7751 Hardware Manual

Tr1
CKIO
Address
RD/
D31–D0
(read)
DACKn
(SA: IO ← memory)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.18 Burst Access Timing in DRAM EDO Mode

RAS Down Mode: The SH7751 Series has an address comparator for detecting row address
matches in burst mode. By using this address comparator, and also setting RAS down mode
specification bit RASD to 1, it is possible to select RAS down mode, in which
asserted after the end of an access. When RAS down mode is used, if the refresh cycle is longer
than the maximum DRAM
maximum value of t
RAS
In RAS down mode, in the event of an access to an address with a different row address, an access
to a different area, a refresh request, or a bus release request,
operation is performed. When DRAM access is resumed after this, since this is the start of RAS
down mode, the operation starts with row address output. Timing charts are shown in figures
13.19 (1), (2), (3), and (4).
Rev. 3.0, 04/02, page 384 of 1064
Tr2 Tc1 Tc2 Tc1
Row c1


assert time, the refresh cycle must be decreased to or below the
.
Tc2 Tc1 Tc2 Tc1
c2
d1 d2


is negated and the necessary
Tc2 Tce Tpc
c8
d8


remains