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Always write to this register prior to accessing the PCI configuration space. After setting a value
in this register, generate the configuration cycle by reading or writing to the PIO data register
(PCIPDR).
Also, a special cycle is issued by setting H'8000FF00 in this register and writing to the PCIPDR.
Bit 31—Configuration Cycle Generate Enable (CFGEN): Indicates the configuration cycle
generation enable.
Bits 30 to 24—Reserved: These bits always return 0 when read. Always write 0 to these bits
when writing.
Bits 23 to 16—PCI Bus No. (BUSNO): These bits specify the No. of the PCI bus subject to
configuration access. Bus No. D indicates the bus connected with the PCIC. The bus No. is
expressed with 8 bits, and its maximum value is 255.
Bits 15 to 11—Device No. (DEVNO): These bits specify the No. of the device subject to
configuration access. The device No. is expressed with 5 bits, and takes a value from bits 0 to 31.
In place of IDSEL, one of bits 31 to 16 of the A/D line, corresponding to the device No. set in this
field, is driven to "1". The following table shows the relationship between the device No. and
IDSEL (A/D [31 to 16]). When the device No. is 10h or greater, A/D [31 to 16]) are all zeros.
DEVNO
IDSEL
H'0
AD[16] = 1 H'4
H'1
AD[17] = 1 H'5
H'2
AD[18] = 1 H'6
H'3
AD[19] = 1 H'7
Bits 10 to 8: Function No. (FNCNO): These bits specify the No. of the function subject to
configuration access. The function No. is expressed with 3 bits, and takes a value of 0 to 7.
Bits 7 to 2—Configuration Register Address (REGADR): These bits set the register subject to
configuration access with a longword boundary.
Bits 1 and 0—Reserved: These bits always return 0 when read. Always write 0 to these bits when
writing.
Rev. 3.0, 04/02, page 866 of 1064
DEVNO
IDSEL
AD[20] = 1 H'8
AD[21] = 1 H'9
AD[22] = 1 H'A
AD[23] = 1 H'B
DEVNO
IDSEL
AD[24] = 1 H'C
AD[25] = 1 H'D
AD[26] = 1 H'E
AD[27] = 1 H'F
DEVNO
IDSEL
AD[28] = 1
AD[29] = 1
AD[30] = 1
AD[31] = 1
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