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However, bus release is not performed during multiple bus cycles generated because the data bus
width is smaller than the access size (for example, when performing longword access to 8-bit bus
width memory) or during a 32-byte transfer such as a cache fill or write-back. In addition, bus
release is not performed between read and write cycles during execution of a TAS instruction, or
between read and write cycles when DMAC dual address transfer is executed. When
is
negated,
is negated and use of the bus is resumed. See appendix D, Pin Functions, for the
pin states when the bus is released.
When a refresh request is generated, the SH7751 Series performs a refresh operation as soon as
the currently executing bus cycle ends. However, refresh operations are deferred during multiple
bus cycles generated because the data bus width is smaller than the access size (for example, when
performing longword access to 8-bit bus width memory) and during a 32-byte transfer such as a
cache fill or write-back, and also between read and write cycles during execution of a TAS
instruction, and between read and write cycles when DMAC dual address transfer is executed.
Refresh operations are also deferred in the bus-released state.
If the synchronous DRAM interface is set to the RAS down mode the PALL command is issued
before a refresh cycle occurs or before the bus is released by bus arbitration.
As the CPU in the SH7751 Series is connected to cache memory by a dedicated internal bus,
reading from cache memory can still be carried out when the bus is being used by another bus
master inside or outside the SH7751 Series. When writing from the CPU, an external write cycle
is generated when write-through has been set for the cache in the SH7751 Series, or when an
access is made to a cache-off area. There is consequently a delay until the bus is returned.
When the SH7751 Series wants to take back the bus in response to an internal memory refresh
request, it negates
. On receiving the
negation, the device that asserted the external
bus release request negates
to release the bus. The bus is thereby returned to the SH7751
Series, which then carries out the necessary processing.
Rev. 3.0, 04/02, page 458 of 1064
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