Hitachi SH7751 Hardware Manual page 1076

Module Register P4 Address
RTC RMINAR H'FFC8 0024 H'1FC8 0024 8
RTC RHRAR H'FFC8 0028 H'1FC8 0028 8
RTC RWKAR H'FFC8 002C H'1FC8 002C 8
RTC RDAYAR H'FFC8 0030 H'1FC8 0030 8
RTC RMONAR H'FFC8 0034 H'1FC8 0034 8
RTC RCR1 H'FFC8 0038 H'1FC8 0038 8
RTC RCR2 H'FFC8 003C H'1FC8 003C 8
RTC RCR3 H'FFC8 0050 H'1FC8 0050 8
RTC RYRAR H'FFC8 0054 H'1FC8 0054 16
INTC ICR H'FFD0 0000 H'1FD0 0000 16
INTC IPRA H'FFD0 0004 H'1FD0 0004 16
INTC IPRB H'FFD0 0008 H'1FD0 0008 16
INTC IPRC H'FFD0 000C H'1FD0 000C 16
INTC IPRD H'FFD0 0010 H'1FD0 0010 16
TMU TOCR H'FFD8 0000 H'1FD8 0000 8
TMU TSTR H'FFD8 0004 H'1FD8 0004 8
TMU TCOR0 H'FFD8 0008 H'1FD8 0008 32
TMU TCNT0 H'FFD8 000C H'1FD8 000C 32
TMU TCR0 H'FFD8 0010 H'1FD8 0010 16
TMU TCOR1 H'FFD8 0014 H'1FD8 0014 32
TMU TCNT1 H'FFD8 0018 H'1FD8 0018 32
TMU TCR1 H'FFD8 001C H'1FD8 001C 16
TMU TCOR2 H'FFD8 0020 H'1FD8 0020 32
TMU TCNT2 H'FFD8 0024 H'1FD8 0024 32
TMU TCR2 H'FFD8 0028 H'1FD8 0028 16
TMU TCPR2 H'FFD8 002C H'1FD8 002C 32
SCI SCSMR1 H'FFE0 0000 H'1FE0 0000 8
SCI SCBRR1 H'FFE0 0004 H'1FE0 0004 8
SCI SCSCR1 H'FFE0 0008 H'1FE0 0008 8
SCI SCTDR1 H'FFE0 000C H'1FE0 000C 8
Area 7 Power-On
1
Address* Size Reset
Held*
Held*
Held*
Held*
Held*
H'00*
H'09*
H'00
Undefined
H'0000*
H'0000
H'0000
H'0000
H'DA74
H'00
H'00
H'FFFF FFFF H'FFFF FFFF Held
H'FFFF FFFF H'FFFF FFFF Held
H'0000
H'FFFF FFFF H'FFFF FFFF Held
H'FFFF FFFF H'FFFF FFFF Held
H'0000
H'FFFF FFFF H'FFFF FFFF Held
H'FFFF FFFF H'FFFF FFFF Held
H'0000
Held
H'00
H'FF
H'00
H'FF
Manual
Reset Sleep
2
Held Held
2
Held Held
2
Held Held
2
Held Held
2
Held Held
2 2
H'00* Held
2 2
H'00* Held
Held Held
Held Held
2 2
H'0000* Held
H'0000 Held
H'0000 Held
H'0000 Held
H'DA74 Held
H'00 Held
H'00 Held
H'0000 Held
H'0000 Held
H'0000 Held
Held Held
H'00 Held
H'FF Held
H'00 Held
H'FF Held
Rev. 3.0, 04/02, page 1037 of 1064
Synchro-
Stand- nization
by Clock
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
2
H'00* Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
H'00 Pclk
H'FF Pclk
H'00 Pclk
H'FF Pclk