Figure 23.48 Dram Bus Cycle: Dram Cas-Before-Ras Refresh (Tras [2:0] = 001, Trc [2:0] = 001) - Hitachi SH7751 Hardware Manual

CKIO
A25–A0
RD/
t
CASD1
D31–D0
(write)
DACKn
(SA: IO ← memory)
DACKn
(SA: IO → memory)
Notes: IO: DACK device
SA: Single address DMA transfer
DA: Dual address DMA transfer
DACK set to active-high
Figure 23.48 DRAM Bus Cycle: DRAM CAS-Before-RAS Refresh
Rev. 3.0, 04/02, page 1004 of 1064
TRr1 TRr2 TRr3
t
AD
t
CSD
t
RWD
t
t
RASD
RASD
t
CASD1
t
WDD
t
DACD
t
DACD
(TRAS [2:0] = 001, TRC [2:0] = 001)
TRr4 TRr4w TRr5
t
RASD
t
CASD1
Trc Trc Trc