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10.8.2
Watchdog Timer Control/Status Register (WTCSR)
The watchdog timer control/status register (WTCSR) is an 8-bit readable/writable register
containing bits for selecting the count clock and timer mode, and overflow flags.
WTCSR is initialized to H'00 only by a power-on reset via the
an internal reset due to WDT overflow. When used to count the clock stabilization time when
exiting standby mode, WTCSR retains its value after the counter overflows.
To write to the WTCSR register, use a word-size access with the upper byte set to H'A5. To read
WTCSR, use a byte-size access.
Bit:
7
TME
Initial value:
0
R/W:
R/W
Bit 7—Timer Enable (TME): Specifies starting and stopping of timer operation. Clear this bit to
0 when using the WDT in standby mode or to change a clock frequency.
Bit 7: TME
0
1
Bit 6—Timer Mode Select (WT/
interval timer.
Bit 6: WT/
0
1
Note: The up-count may not be performed correctly if WT/
Bit 5—Reset Select (RSTS): Specifies the kind of reset to be performed when WTCNT
overflows in watchdog timer mode. This setting is ignored in interval timer mode.
Bit 5: RSTS
0
1
6
5
WT/
RSTS
0
0
R/W
R/W
Description
Up-count stopped, WTCNT value retained
Up-count started
): Specifies whether the WDT is used as a watchdog timer or
Description
Interval timer mode
Watchdog timer mode
Description
Power-on reset
Manual reset
4
3
WOVF
IOVF
0
0
R/W
R/W
is modified while the WDT is running.
Rev. 3.0, 04/02, page 255 of 1064
pin. It retains its value in
2
1
CKS2
CKS1
0
0
R/W
R/W
(Initial value)
(Initial value)
(Initial value)
0
CKS0
0
R/W
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