Figure 15.24 Receive Data Sampling Timing In Asynchronous Mode - Hitachi SH7751 Hardware Manual

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5
Base clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing

Figure 15.24 Receive Data Sampling Timing in Asynchronous Mode

The receive margin in asynchronous mode can therefore be expressed as shown in equation (1).
M = (0.5 –
2N
M: Receive margin (%)
N: Ratio of clock frequency to bit rate (N = 16)
D: Clock duty cycle (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
From equation (1), if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation (2).
When D = 0.5 and F = 0:
M = (0.5 – 1/(2  16))  100% = 46.875% ............................................ (2)
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Rev. 3.0, 04/02, page 630 of 1064
16 clocks
8 clocks
–7.5 clocks
Start bit
1 | D – 0.5 |
) – (L – 0.5) F –
+7.5 clocks
D0
(1 + F) × 100%
N
................. (1)
D1