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These possibilities are shown in the individual instruction descriptions. All exception events
that originate in the FPU are assigned as the same exception event. The meaning of an
exception is determined by software by reading system register FPSCR and interpreting the
information it contains. If no bits are set in the FPU exception cause field of FPSCR when one
or more of bits O, U, I, and V (in case of FTRV only) are set in the FPU exception enable
field, this indicates that an actual FPU exception is not generated. Also, the destination register
is not changed by any FPU exception handling operation.
Except for the above, the bit corresponding to V, Z, O, U, or I is set to 1 in all processing, and
the default value is generated as the result of the operation.
Invalid operation (V): qNAN is generated as the result.
Division by zero (Z): Infinity with the same sign as the unrounded value is generated.
Overflow (O):
In round to zero mode, the maximum normalized number, with the same sign as the
unrounded value, is generated.
In round to nearest mode, infinity with the same sign as the unrounded value is generated.
Underflow (U):
When FPSCR.DN = 0, a denormalized number with the same sign as the unrounded value,
or zero with the same sign as the unrounded value, is generated.
When FPSCR.DN = 1, zero with the same sign as the unrounded value, is generated.
Inexact exception (I): An inexact result is generated.
6.6
Graphics Support Functions
The SH7751 Series supports two kinds of graphics functions: new instructions for geometric
operations, and pair single-precision transfer instructions that enable high-speed data transfer.
6.6.1
Geometric Operation Instructions
Geometric operation instructions perform approximate-value computations. To enable high-speed
computation with a minimum of hardware, the SH7751 Series ignores comparatively small values
in the partial computation results of four multiplications. Consequently, the error shown below is
produced in the result of the computation:
Maximum error = MAX (individual multiplication result
–MIN (number of multiplier significant digits–1, number of multiplicand significant digits–1)
2
The number of significant digits is 24 for a normalized number and 23 for a denormalized number
(number of leading zeros in the fractional part).
In future version of SuperH series, the above error is guaranteed, but the same result as SH7751
Series is not guaranteed.
Rev. 3.0, 04/02, page 164 of 1064
) + MAX (result value
–23
–149
2
, 2
)
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