Timer Control Registers (Tcr) - Hitachi SH7751 Hardware Manual

The TCNT registers in channels 3 and 4 are initialized to H'FFFFFFFF by a power-on reset, but
are not initialized and retain their contents by a manual reset or in standby mode.
Bit: 31
Initial value: 1
R/W: R/W
In channels 0 to 2, when the input clock is the on-chip RTC output clock (RTCCLK), TCNT
counts even in module standby mode (that is, when the clock for the TMU is stopped). When the
input clock is the external clock (TCLK) or internal clock (P
standby mode.
12.2.6

Timer Control Registers (TCR)

The TCR registers are 16-bit readable/writable registers. There are five TCR registers, one for
each channel.
Each TCR selects the count clock, specifies the edge when an external clock is selected in
channels 0 to 2, and controls interrupt generation when the flag indicating timer counter (TCNT)
underflow is set to 1. TCR2 is also used for channel 2 input capture control, and control of
interrupt generation in the event of input capture.
The TCR registers in channels 0 to 2 are initialized to H'0000 by a power-on or manual reset, but
are not initialized in standby mode.
The TCR registers in channels 3 and 4 are initialized to H'0000 by a power-on reset, but are not
initialized by a manual reset or in standby mode.
1. Channel 0 and 1 TCR bit configuration
Bit: 15
—
Initial value: 0
R/W: R
Bit: 7
—
Initial value: 0
R/W: R
Rev. 3.0, 04/02, page 294 of 1064
30 29
· · · · · · · · · · · · ·
1 1
R/W R/W
14 13
— —
0 0
R R
6 5
— UNIE CKEG1
0 0
R R/W R/W
R/W

), TCNT contents are retained in
12 11 10
— —
0 0
R R
4 3
CKEG0 TPSC2
0 0
R/W R/W
2 1
1 1
R/W R/W
9
— — UNF
0 0
R R R/W
2 1
TPSC1 TPSC0
0 0
R/W R/W
0
1
8
0
0
0