Table 13.10 8-Bit External Device/Big-Endian Access and Data Alignment
Operation
Access
Size
Address No. D31–D24 D23–D16 D15–D8 D7–D0
Byte
n
1
Word
2n
1
2n+1
2
Long-
4n
1
word
4n+1
2
4n+2
3
4n+3
4
Quad-
8n
1
word
8n+1
2
8n+2
3
8n+3
4
8n+4
5
8n+5
6
8n+6
7
8n+7
8
Rev. 3.0, 04/02, page 362 of 1064
Data Bus
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,
,
DQM3
DQM2
Data
7–0
Data
15–8
Data
7–0
Data
31–24
Data
23–16
Data
15–8
Data
7–0
Data
63–56
Data
55–48
Data
47–40
Data
39–32
Data
31–24
Data
23–16
Data
15–8
Data
7–0
Strobe Signals
,
,
,
,
,
DQM1
DQM0
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
Asserted
,