Hitachi SH7751 Hardware Manual page 852

Bits 31 to 27, 24, 8 to 6, and 2 to 0 can be written to from both the PP and PCI buses. However,
bits 31 to 27 and 24 are write-clear bits that are cleared when 1 is written to them. Bits 22 and 21
can be written to from the PP bus. Other bits are fixed in hardware.
The PCICONF1 register is initialized to H'02900080 at a power-on reset or software reset.
Always write to this register before initiating transfers on the PCI bus.
Bit 31—Parity Error Detection Status (DPE): Indicates the detection of a parity error in read
data when the PCIC is operating as the master, or a party error in write data when the PCIC is
operating as a target.
Bit 31: DPE
0
1
Bit 30—System Error Output Status (SSE): Indicates the
Bit 30: SSE
0
1
Bit 29—Master abort receive status (RMA): Indicates the termination of transaction by master
abort when the PCIC is operating as the master.
Bit 29: RMA
0
1
Bit 28—Target Abort Receive Status (RTA): Indicates the termination of transaction by master
abort when the PCIC is operating as the master.
Bit 28: RTA
0
1
Bit 27—Target Abort Execution Status (STA): Indicates the termination of transaction by target
abort when the PCIC is operating as the target.
Description
No parity error detected by device
Parity error detected by device
Set this bit regardless of the parity error response bit (bit 6) on the device
Description



Device not asserting



Device asserting
Description
No transaction termination using bus master abort
Detection by bus master of transaction termination by bus master abort
However, in the case of a master abort in a special cycle, notify the master
devices that are not set
Description
No transaction termination using target abort
Detection by bus master of transaction termination by target abort

assert operation of the PCIC.
(Value retained until cleared)
Rev. 3.0, 04/02, page 813 of 1064
(Initial value)
(Initial value)
(Initial value)
(Initial value)