Figure 13.46 Wait Timing For Pcmcia Memory Card Interface - Hitachi SH7751 Hardware Manual

Tpcm0 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w
CKIO
A25–A0
REG
RD/
(read)
D15–D0
(read)
(write)
D15–D0
(write)
DACKn
(DA)
Note: For DACKn, an example is shown where CHCRn.AL (access level) = 0 for the DMAC.

Figure 13.46 Wait Timing for PCMCIA Memory Card Interface

Rev. 3.0, 04/02, page 428 of 1064