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Bit 4: O/
0
1
Notes: *1 When even parity is set, parity bit addition is performed in transmission so that the total
number of 1-bits in the transmit character plus the parity bit is even. In reception, a
check is performed to see if the total number of 1-bits in the receive character plus the
parity bit is even.
*2 When odd parity is set, parity bit addition is performed in transmission so that the total
number of 1-bits in the transmit character plus the parity bit is odd. In reception, a check
is performed to see if the total number of 1-bits in the receive character plus the parity
bit is odd.
Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length.
Bit 3: STOP
0
1
Notes: *1 In transmission, a single 1-bit (stop bit) is added to the end of a transmit character
before it is sent.
*2 In transmission, two 1-bits (stop bits) are added to the end of a transmit character
before it is sent.
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
Bit 2—Reserved: This bit is always read as 0, and should only be written with 0.
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the on-
chip baud rate generator. The clock source can be selected from P
according to the setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 16.2.8, Bit Rate Register (SCBRR2).
Bit 1: CKS1
Bit 0: CKS0
0
0
1
1
0
1
Note: P : Peripheral clock
Rev. 3.0, 04/02, page 640 of 1064
Description
1
Even parity*
2
Odd parity*
Description
1
1 stop bit*
2
2 stop bits*
Description
P clock
P /4 clock
P /16 clock
P /64 clock
(Initial value)
(Initial value)
, P
/4, P
/16, and P
(Initial value)
/64,
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