Pci Interrupt Mask Register (Pciintm) - Hitachi SH7751 Hardware Manual

Bit 1—Master Write

received from the target while writing data to the target. Detects only when bit 6 (PER) of
the PCICONF1 is 1.
Bit 0—Master Read Data Parity Error Interrupt (M_DPERR_RD): When the PCIC is master,
a parity error was detected during a data read from the target. Detects only when bit 6 (PER) of the
PCICONF1 is 1.

22.2.21 PCI Interrupt Mask Register (PCIINTM)

Bit: 31
—
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
Bit: 23
—
Initial value: 0
PCI-R/W: R
PP Bus-R/W: R
Bit: 15
M_LOCK
ON
Initial value: 0
PCI-R/W: R/W
PP Bus-R/W: R/W
Bit: 7
ADRPER
R
Initial value: 0
PCI-R/W: R/W
PP Bus-R/W: R/W
The PCI interrupt mask register (PCIINTM) sets the respective interrupt masks for the interrupts
generated when errors occur in PCI transfers. It is a 32-bit read/write register that can be accessed
Rev. 3.0, 04/02, page 848 of 1064
    
Detection Interrupt (M_DPERR_WT): When the PCIC is master.
30 29
— —
0 0
R R
R R
22 21
— —
0 0
R R
R R
14 13
T_TGT_A —
BORT
0 0
R/W R
R/W R
6 5
SERR_D T_DPER
ET R_WT
0 0
R/W R/W
R/W R/W
28 27
— —
0 0
R R
R R
20 19
— —
0 0
R R
R R
12 11
— —
0 0
R R
R R
4 3
T_PERR_ M_TGT_A M_MST_
DET BORT
0 0
R/W R/W
R/W R/W
26 25
— —
0 0
R R
R R
18 17
— —
0 0
R R
R R
10 9
— TGT_RET MST_DIS
RY
0 0
R R/W
R R/W
2 1
M_DPER M_DPER
ABORT R_WT
0 0
R/W R/W
R/W R/W
24
—
0
R
R
16
—
0
R
R
8
0
R/W
R/W
0
R_RD
0
R/W
R/W