Figure 22.16 Target Memory Read Cycle In Host Mode (Burst, With Stepping) - Hitachi SH7751 Hardware Manual

PCICLK
AD31–AD0
PAR
C/ –C/
Addr: PCI space address
Dn: nth data
AP: Address parity
DPn: nth data parity
Com: Command
BEn: nth data byte enable

Figure 22.16 Target Memory Read Cycle in Host Mode (Burst, With Stepping)

Addr
AP
Com
BE0
D0
DP0 DPn-1
Rev. 3.0, 04/02, page 909 of 1064
Dn
DPn
BEn