Hitachi SH7751 Hardware Manual page 295

Bit 4—Watchdog Timer Overflow Flag (WOVF): Indicates that WTCNT has overflowed in
watchdog timer mode. This flag is not set in interval timer mode.
Bit 4: WOVF
0
1
Bit 3—Interval Timer Overflow Flag (IOVF): Indicates that WTCNT has overflowed in
interval timer mode. This flag is not set in watchdog timer mode.
Bit 3: IOVF
0
1
Bits 2 to 0—Clock Select 2 to 0 (CKS2–CKS0): These bits select the clock used for the WTCNT
count from eight clocks obtained by dividing the frequency divider 2 input clock*. The overflow
periods shown in the following table are for use of a 33 MHz input clock, with frequency divider 1
off, and PLL circuit 1 on (
Note: * When PLL1 is switched on or off, the clock following the switch is used.
Bit 2: CKS2 Bit 1: CKS1
0 0
1
1 0
1
Note: The up-count may not be performed correctly if bits CKS2–CKS0 are modified while the
WDT is running. Always stop the WDT before modifying these bits.
Rev. 3.0, 04/02, page 256 of 1064
Description
No overflow
WTCNT has overflowed in watchdog timer mode
Description
No overflow
WTCNT has overflowed in interval timer mode

6).
Bit 0: CKS0
0
1
0
1
0
1
0
1
Description
Clock Division Ratio
1/32 (Initial value)
1/64
1/128
1/256
1/512
1/1024
1/2048
1/4096
(Initial value)
(Initial value)
Overflow Period

41 s

82 s

164 s

328 s

656 s
1.31 ms
2.62 ms
5.25 ms