Hitachi SH7751 Hardware Manual page 1077

Module Register P4 Address
SCI SCSSR1 H'FFE0 0010 H'1FE0 0010 8
SCI SCRDR1 H'FFE0 0014 H'1FE0 0014 8
SCI SCSCMR1 H'FFE0 0018 H'1FE0 0018 8
SCI SCSPTR1 H'FFE0 001C H'1FE0 001C 8
SCIF SCSMR2 H'FFE8 0000 H'1FE8 0000 16
SCIF SCBRR2 H'FFE8 0004 H'1FE8 0004 8
SCIF SCSCR2 H'FFE8 0008 H'1FE8 0008 16
SCIF SCFTDR2 H'FFE8 000C H'1FE8 000C 8
SCIF SCFSR2 H'FFE8 0010 H'1FE8 0010 16
SCIF SCFRDR2 H'FFE8 0014 H'1FE8 0014 8
SCIF SCFCR2 H'FFE8 0018 H'1FE8 0018 16
SCIF SCFDR2 H'FFE8 001C H'1FE8 001C 16
SCIF SCSPTR2 H'FFE8 0020 H'1FE8 0020 16
SCIF SCLSR2 H'FFE8 0024 H'1FE8 0024 16
H-UDI SDIR H'FFF0 0000 H'1FF0 0000 16
H-UDI SDDR H'FFF0 0008 H'1FF0 0008 32
Hi-UDI SDINT H'FFF0 0014 H'1FF0 0014 16
Notes: *1 With control registers, the above addresses in the physical page number field can be
accessed by means of a TLB setting. When these addresses are set directly without
using the TLB, operations are limited.
*2 Includes undefined bits. See the descriptions of the individual modules.
*3 Use word-size access when writing. Perform the write with the upper byte set to H'5A or
H'A5, respectively. Byte- and longword-size writes cannot be used.
Use byte-size access when reading.
Rev. 3.0, 04/02, page 1038 of 1064
Area 7 Power-On
1
Address* Size Reset
H'84
H'00
H'00
H'00*
H'0000
H'FF
H'0000
Undefined
H'0060
Undefined
H'0000
H'0000
H'0000*
H'0000
H'FFFF*
Held
H'0000
Manual
Reset Sleep
H'84 Held
H'00 Held
H'00 Held
2 2
H'00* Held
H'0000 Held
H'FF Held
H'0000 Held
Undefined Held
H'0060 Held
Undefined Held
H'0000 Held
H'0000 Held
2 2
H'0000* Held
H'0000 Held
2
Held Held
Held Held
Held Held
Synchro-
Stand- nization
by Clock
H'84 Pclk
H'00 Pclk
H'00 Pclk
2
H'00* Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk
Held Pclk